1. Field of the Invention
The instant invention relates to a Finite Impulse Response filter that filters complex digital signals in a manner such that the real and imaginary parts of a complex digital signal are filtered separately in distinct parallel data paths. The filter is adaptive in that it includes circuitry that will update the multiplicands used as the complex weights used in the filtering process, and load them into the filter without interrupting or terminating the filtering process.
2. Discussion of the Prior Art
There presently exist numerous electrical and electronic devices that make use of microprocessors to process sampled data. The typical data operations required of the microprocessor includes multiplication, addition, subtraction, logical AND and OR, and repetitive combinations thereof, for e.g. multiply and divide. Though microprocessors are particularly useful for applications where speed and data handling size are not critical, they are not suitable for many data intensive applications. For instance, in radar and sonar systems, medical imaging systems, and speech recognition systems, huge amounts of data are usually required to be processed at fast speeds. For a typical microprocessor, a single multiply-accumulate operation may take as long as 25 clock cycles. To increase the processing speeds, a number of these systems now incorporate digital signal processors (DSP) processors which are microprocessors having architectures that are optimized to process the sampled data at high rates. The architecture of a DSP is designed to exploit the repetitive nature of signal processing. Thus, a DSP having a fast array multiplier and accumulator may execute the single multiply-accumulate operation in a single clock cycle.
The DSP chip may be utilized as an application-specific device that can perform one function more accurately, faster, and more cost-effectively. For example, an increasing number of digital filter and Fourier transform applications require DSP chips. A special type of digital filter, a Finite-Impulse-Response ("FIR") filter, i.e., a filter that is characterized as having an impulse response of finite length, is ideally used to achieve exact linear (or near linear) phase response. Ideally this is used in systems where it is paramount that the phase affects the shape of the output of the FIR filter by, at most, a time delay. In radar systems incorporating phased-array antennas, for example, digital FIR filters are required to process complex digital signals, i.e., signals having real and imaginary components. Usually, the filter functions to get rid of noise caused by antenna mismatch or clutter. When filtering complex digital signals, the real and imaginary parts of the digital signal and their time delayed versions are each multiplied by a complex weight and the results are then summed. To perform the filtering function, both real and imaginary parts of the weight and the negative of the imaginary part of the weight, must be made available as multiplicands (coefficients). Most digital filters are thus conveniently implemented using DSP chips having coefficient multiplier elements, adders or summing devices, and delay elements (memory storage devices). The filter is considered "adaptive" when the coefficients are variable and updated by a host processor that implements an updating algorithm.
There are presently available integrated circuit chips that are used for filtering digital signals. For instance, the INMOS signal processing chip IMSA100 is able to do up to 32 parallel multiplies and additions (or subtractions) and that makes it useful as a FIR filter. This particular DSP filter is designed for use in a microprocessor system, so that the coefficients may be loaded through an input port to one or two banks of registers or alternatively, to external ROM or RAM. When filtering real data, one bank of memory is used to provide the coefficients for the filter. For adaptive filtering, one bank of memory is used while the other is being updated with new coefficients. For complex adaptive filtering however, the two bank architecture becomes unusable, even at low data rates. This is because both banks of coefficients are required to produce the filter output, i.e., one bank produces the real output and the other produces the imaginary output. To update the coefficients, the filtering process has to be stopped while the new coefficients are being loaded in. Usually, the time required to load new coefficients is long compared to the data rate of most existing processors. In fact, most existing processors can do complex processing at only one-half the data rate.
To alleviate excessive delays in updating the coefficients, alternative designs have been implemented where the coefficients are accessed circularly from an external memory. Using appropriate control circuitry, one bank of memory can provide the coefficients to the filter while the other bank of memory is being updated. This arrangement relieves the updating problem but it does not take full advantage of the geometry of the complex filter and requires a significant amount of external control circuitry.
Additionally, in order to properly perform adaptive filtering, an error signal, which is calculated as the sum of the filter output signal and a "desired" input signal, must be provided as an output to the host processor to calculate the updated weight coefficients. Present DSP processors do not provide this capability and external adder circuitry is usually required to calculate the error for updating the weights. The need for an external adder and corresponding control circuitry degrades filter performance and takes up valuable circuit board area.
Most of the available FIR filter chips also require the need to fix and truncate the floating point result coming out of the host processor. This is due to the fact that the internal processing is not floating point. One consequence of this, is that the dynamic range usually required for adaptive processing, is not preserved.
In view of the foregoing limitations of the present generation of adaptive FIR filters, there exists the need for a complex adaptive FIR filter that can process complex digital signals more quickly and efficiently when the signal to be processed is a complex digital data and when the processing speed requirements of the data rate make commercially available FIR filter chips functionally prohibitive.
Therefore, it is the objective of the instant invention to provide a complex adaptive FIR filter having an internal processing architecture that features two parallel data paths, one which filters the real data stream of the complex signal and another which filters the complex data stream whereby the architecture takes maximum advantage of the time available to do the required calculations.
It is a further objective to provide a complex adaptive FIR filter that is able to do complex adaptive digital filtering without having to interrupt or stop the filtering process when the weight coefficients are being updated.
It is another object of the invention to provide a complex adaptive FIR filter having an input for receiving a "desired" input signal and an adder element for enabling the generation of an error signal for more efficient adaptive filter implementation.
Another objective of the present invention is to provide a complex adaptive FIR filter that incorporates floating-point processing to preserve the dynamic range required for adaptive processing.
It is still another objective to provide a complex adaptive FIR filter that is designed as a standalone device that requires no external circuitry to interface to a host processor.
Still another objective is to provide a complex adaptive FIR filter that can be cascaded to allow the creation of longer filters for applying longer coefficient sets to the data stream.
Yet another objective of the present invention is to provide a complex adaptive FIR filter that provides a unique and efficient way to update the weight coefficients without having to provide significant amounts of hardware support.